1. Field of the Invention
The present invention relates to an integrated circuit and control method thereof and, more particularly, to reset operation control of a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, a semiconductor integrated circuit which can further reduce power consumption is demanded so as to drive a battery use device for a longer period of time and in consideration of environmental problems. The power consumption of the semiconductor integrated circuit can be classified into a dynamic electric power required for operations and a static electric power required only upon connection of a power source. Since these electric powers are consumed based on different principles, different power saving techniques are respectively used for them.
The dynamic electric power is consumed by currents which flow upon charging/discharging parasitic capacitances caused by signal changes, and currents such as through currents which flow at the time of switching. Therefore, by suppressing signal changes within a trouble-free range of functional operations, the dynamic electric power can be reduced. As a typical power saving method based on such principle, “clock gating” is available, and is popularly used currently.
On the other hand, the static electric power is consumed by charges stored in parasitic capacitances and leak currents. Upon miniaturization of processes, the parasitic capacitances tend to be decreased, but leak currents tend to be increased. Especially, as a polysilicon gate oxide film is thinner, leak currents are exponentially increased at one time. In order to reduce the leak currents, a method of controlling voltages, for example, a power shutoff method is effective. For example, a power switch is arranged between a target circuit and power source, and is controlled to shut off the power source. Even now, the leak currents keep increasing tendency, and the power shutoff control is also important for reducing a power.
However, upon execution of voltage control, initialization is usually required after return, that is, a reset operation usually has to be made before starting an operation. In the reset operation, in order to actively control memory elements such as flip-flops to cause signal changes, clock gating is normally not performed. For this reason, during the reset operation, a larger electric power tends to be consumed than a normal operation status.
In order to suppress power consumption during the reset operation, a method of shortening a reset operation period and a method of lowering an operating ratio are known. For example, Japanese Patent Laid-Open No. 2002-312073 discloses a method of optimizing a time after power ON until reset cancelation by recording a reset cancel timing in a register corresponding to a power shutoff region. Also, Japanese Patent Laid-Open Nos. 2001-101764 and 10-320072 disclose a method of lowering an operating ratio by lowering a clock frequency until a reset signal is negated at a reset timing.